SEU sensitivity of Junctionless Single-Gate SOI MOSFETs-based 6T SRAM cells investigated by 3D TCAD simulation
نویسندگان
چکیده
Article history: Received 25 May 2015 Received in revised form 20 June 2015 Accepted 24 June 2015 Available online xxxx
منابع مشابه
Kharkov National University of Radioelectronics
Single event upsets (SEU) produced by heavy ions in SOI CMOS SRAM cells were simulated using a mixed-mode approach, that is, two-dimensional semiconductor device simulation by TCAD tool coupled with circuit SPICE simulator. The effects of parasitic BJT and particle strike position on the SOI CMOS SRAM cells upset for transistor length scaling from 0.25 um to 65nm are presented.
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عنوان ژورنال:
- Microelectronics Reliability
دوره 55 شماره
صفحات -
تاریخ انتشار 2015